Basic SV and UVM Questions
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Throughput vs latency in computer architecture.
1. What is setup, hold time. Reason of metastability. 2. How to reduce setup time, hold time. 3. A C code to check if a given number is divisible by 2 4. Difference between mealy and moore machine 5. Project and resume based questions
Questions based on CV mostly questions are from SV, UVM, Protocols
tell me the UVM testbench execution flow
How would you write a testplan for a FIFO? Create an AND gate from NAND gates. How do you select 2 values from an array whose sum is some value p in linear time?
1 easy and 1 medium level leet code problem along with unit test and expected output of a program.
Describe the testbench hierarchy in UVM
1. what is the alternate for analyis port 2. related to fork join 3. interrupt handling
Tips for round 2- keep your basics strong. Don't need much. Just got get played by interviewers. If you're stuck or don't know the answer. Atleast try for an approach and keep asking for feedback. Before solving any question, explain your approach and then proceed. Your behaviour shouldn't be like digital systems, either 0 or 1. It should be like analog. Keep explaining every step. And don't say anything that you can't explain. Tips for round 3- Just don't lie. Speak the truth. Don't mention GATE scores in CV. Deny any further studies plan from your side. Just say that you'll do it if your firm wants you to upgrade your skills and be more productive for firm. Else you have no plans. Preferred location - Always say Noida.
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