Constraints, p_sequencer, m_sequencer, tb flow, agent
Design Verification Engineer Interview Questions
1,113 design verification engineer interview questions shared by candidates
set up time, hold time
Describe your previous work experience
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
Questions were from resume. How will you verify a 32 bit ALU unit having 2 inputs is working fine for all 2^32 * 2^32 combinations?
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
FIFO depth, and ASYNC FIFO test plan
Questions on pipelining
What is stuck at fault, transition fault, bridging fault?
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