Design, Test plan, SystemVerilog ......
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
how to resolve the issue with a malfunctioning vending machine with a pending deadline
Delayed assignment and delayed evaluation in Verilog
What is an isolation cell?
Sorting, bit logic
How do you find common elements between the arrays? reduce the complexity, asked me to write the code
What is the scope of a static variable? Given multiple scenarios(static variables across files, in recursion, ect.)
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
class A; function int foo(); int a; return ++a; endfunction endclass program tb; A a; int b, c; initial begin for(int i = 0; i < 10; i++) begin b = a.foo(); c = foo(); $display("B = %0d", b); $display("C = %0d", c); end end function int foo(); int a; return ++a; endfunction
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