1. Verification process 2. Test plan 3. UVM and System verilog - logic, coding questions, UVM_Info
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Are you willing to work on a shifting schedule?
Do we run a sweatshop or do we play
Basic questions about verilog and system verilog
Can you just Introduce yourself
What is the reason you go for a PVT on SoC and what is the criteria you need to consider for validating the SoC
What is synchronous and asynchronous reset? Setup time and hold time
How do you handle the arbitration for multi master and multi slave in apb protocol
About BTech project and basic digital Electronics
Basics of digital verilog projects and academics project
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