The horse race question( minimum times of finding the first 5 horses)
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Phone questions: How to get the same rise and fall time for an inverter? What’s a LPF/HPF? What's the step response output of a LPF and HPF? What's Nyquist criterion? What's aliasing? What's impulse? Why do we measure impulse response? What is oversampling and why do we do it? What is FFT? IIR and FIR filters? What is quantization and quantization error? What's the difference between struct and a class? What is inheritance - explain. What did you model in real numbers? Did you find any bugs with your real number modeling? Onsite questions: Almost all the rounds started off with what I worked on. There was one round where they gave a problem to code and get it to compile - it was a difference detector which has input data coming in on every clock cycle. If data difference is +1 issue pos_signal; -1 issue neg_signal and others error_signal. They were unable to explain the requirements properly and left me confused on the specifics of the design given such a short time span. This round didn't go well. What's your dream job why? Asked about usage of randomization and classes. Not a single question on OVM/UVM though the job role specifies its heavy use in the role. What's the most complex sequence that you wrote? How would you call a testing done.
There were no difficult questions.
Some computer architecture questions like pipeline design and pipeline hazards
Python question and verilog question to implement the same thing
introduce your last position/ project?
In first round basic timing questions related to setup and hold time, Object oriented programming concepts and basic scripting etc. In second round one design problem and cross questions on it.
1. write assetions to find the numers which are 2 powers.ex 2^0,2^1.....? 2.design counters for different scenarios like desing mod 15 counter but it should skip counting 0,3,4,8,5
Round 1: resume projects(in detail, my role and contribution), basics like cmos inverter, cmos nand gate, current mirror, blocking vs non blocking, explained a design and asked for the verilog code of it. Round 2: Linux, Python regular expressions. I could not answer linux and python questions so he asked me to explain the logic instead of writing the code. 45 mins break Round 3: She wanted to know how well I was aware of Analog design basics. Virtual interface, inertial vs transport delay, how to debug errors in simulator, asked about the tools I mentioned in the resume. Round 4: Lots of verilog, digital basics, gave a black box and asked how can I verify it if there were two sub modules one analog and one digital. Clock gating and how can we get clock gating, basic building block of counters, inertial vs transport delay, verilog vs SV, . Round 5: It was more like a discussion on a verification plan with analog and digital modules. Round 6: With the manager, behavioral questions, how do you deal with stress, how did you manage people in your previous job, how do you deal with people who always comment, why do you want to get hired for this role even though you do not have enough skills.
Verilog code for the clock divider Verilog code for clock generator for a particular frequency Same basic Verilog and System Verilog questions.
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