Medium difficult
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Why are Verification Models written in C?
Describe your projects.
what are different phases in UVM and why we are using phases in UVM
Coding Puzzles, Verification Basics questions related to TB
TDM (time division multiplexing) working and its corner cases .. FIFO questions
FSM, timing issue, perl
Full adder code, Gave some verilog codes to debug and find errors, Digital questions and Aptitude is important
UVM, SV concepts
: first given a block which you can see its interface and what would you check in order to make sure that the component works as it should the component was something like a memory. second question is a simple leet code question.
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