Computer Architecture, Logic design, validation, software, behavioral.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
They asked about mu uvm design verification project
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Questions about debug of failure
power integrity understanding: including impedance threshold define and theory.
Self-assessment, technical skills and soft skills
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