nand gate using 2x1 mux
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Why do we use virtual sequence. Virtual interface.
The first thing was a phone call with the recruiter where he asked questions like my interests, past experience, graduation date, etc. In the coding round 1: SystemVerilog FSM question + behavioral Then the coding round 2: Python question + behavioral
What does functional coverage is 70% and code coverage 100% means?
asked to draw half adder .number conversions were asked
what would happen in the following case? class my_class ; endclass my_class my_object; my_class array[N:1]; my_object=new (); for (i=0;i<N;i++) array[i] = my_object;
How do I reduce power at the system level?
design mod 4 counter using T flipflop design a fulladder using logic gates
Design a mod 5 counter
use C++ to write a function reverse a linked list
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