Explain about FIFO, Clk generation, State machine
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Given an array of N elements and an array of M elements, both sorted in ascending order, create an array C that combines A and B in ascending order.
On projects and sv uvm based Protocol knowledge on what we mentioned in resume
Asked me to tell about myself, past work I’ve done, what do I expect from my new team, manager, etc.
Questions on interface, clocking blocks, assertions, uvm, X propagation.
Dont remember much but mostly code deep dives and situational questions related to work.
Describe what a virtual function does?
I was asked to write system verilog constraints for a variety of random stimulus needs.
Register renaming
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
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