All basic pipelining, hazards and their types, prevention techninques.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
What is your experience with random constrained stimulus?
The asked about past work experience.
completely based on system verilog and digital design concepts
Talk about resume, explain the detail. ask some related questions on the project.
Basics of UVM and SV
Grilled on my current work, System Verilog basics, UVM in depth, Comp Arch questions like Cache coherency.
Should be ready to write some logic (C/Verilog/System Verilog) on the spot
Energy - cost - time trade offs
The manufacturing Process of a chip from start to end
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