2 rounds of Interview happened on the same day on call. Asked to code the monitor for a DUT. DUT was loaded with all the conditions with how it works which made it complex. SV constraint and some algorithm related questions were asked. All were of good quality.
Synchronous FIFO (based on the project), Memory design, C programming questions
static timing analysis
network theory
Define verilog ,systemverilog. Memory /cache
DSP, OOPs Concepts, Basics CMOS based concepts
Just asked basic questions on DSP - upsampling and downsampling
What is the difference between SV function and Verilog function?
Design Nand Gate using CMOS?
The first round had questions based on signal processing, basics of system Verilog, and I was given a take-home coding task to write an RTL code to check if there is an increment, decrement by 1 bit and if not, print error; and verify the same using a class-based testbench.
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