Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
Clock domain crossings and reset domain crossings
Wie funktionieren Flip Flops? Wie funktioniert SerDes?
What is a fpga and what is a lookup table?
Some code test. Some system knowledge test.
Es war ein technisches Vorstellungsgespräch, bei dem vor allem Fragen zum Lebenslauf gestellt wurden,
What greek philosopher didn't write any of his works?
Verilog code for shift register.
How to determine if a taped out chip failed hold/setup timing
UVM, Functional Verifications, Personal skills questions and pass experiences.
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