What is setup time and hold time?
Digital Design Engineer Interview Questions
820 digital design engineer interview questions shared by candidates
Enlist the relative and absolute timing parameters of an inverter?
Complete digital design like sequential circuits and combinational circuit
Do you know what Inmagine does?
Design Challenge
Memory organization - build 64kb x 64-bit memory using (1.) 32kb x 16 bit and (2.) 16kb x 64bits.
Design FSM for an elevator going between Floor 1 and Floor 2 with buttons inside the elevator to go to the floors and sensors at each floor to sense whether the elevator has reached the floor.
logic design question setip hold time
scripting language code
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.
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