1. Tell me something about yourself. 2. Design a gate level circuit for given specification- To find even and odd no from 0 to 8 decimal no.(without using Kmap). 3. Rate yourself in Verilog. Write Verilog code for 2:1 mux then asked the difference between assign and always. 4. Explain the project of asic design of up counter(steps of rtl coding,floorplan,PnR,CTS,STA). 5. From project of D flip flop layout they asked me about DRC rule. 6. Asked me to draw structure of FinFet and then explain it. 7. Asked me to draw nmos and pmos and explain the difference. 8. What is the difference between short channel and long channel mosfet. 9. What is Floorplan and explain any algorithm. 10. Explain the setup and hold time in latch.
Digital Design Engineer Interview Questions
820 digital design engineer interview questions shared by candidates
given a arbiter, a FIFO, 4 inputs, One flop how will you design a 4 stage pipeline structure.
design cycle and verification plan, polymorphism, inheritance, diff between python and perl, which to use when, blocking vs non blocking assignment, X vs Z in verilog, UVM phases, scoreboard vs monitor, etc
tell me about your previous experience
Tell me about a time that you learned a new skill.
Was asked to describe Projects in Resume,FIR vs IIR, Sampling theorem
Are you fine with doing thing repetitively?
Questions related to Basic Digital Design, Clock Dividers, Clock Domain Crossing(Very imp!!), RTL coding, FSMs, Valid - Ready protocols, Synthesis, Static timing analysis, Physical Design Fundamentals, Little bit Architecture, very basic analog touch up (easy), very few DSP related questions(easy)
Tell me about yourself? What you have done in RTL design Projects?
Design logic using 2:1 mux
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