What's the 2 principle of Cache.
Digital Design Engineer Interview Questions
820 digital design engineer interview questions shared by candidates
1. Tell me something about yourself. 2. Design a gate level circuit for given specification- To find even and odd no from 0 to 8 decimal no.(without using Kmap). 3. Rate yourself in Verilog. Write Verilog code for 2:1 mux then asked the difference between assign and always. 4. Explain the project of asic design of up counter(steps of rtl coding,floorplan,PnR,CTS,STA). 5. From project of D flip flop layout they asked me about DRC rule. 6. Asked me to draw structure of FinFet and then explain it. 7. Asked me to draw nmos and pmos and explain the difference. 8. What is the difference between short channel and long channel mosfet. 9. What is Floorplan and explain any algorithm. 10. Explain the setup and hold time in latch.
given a arbiter, a FIFO, 4 inputs, One flop how will you design a 4 stage pipeline structure.
design cycle and verification plan, polymorphism, inheritance, diff between python and perl, which to use when, blocking vs non blocking assignment, X vs Z in verilog, UVM phases, scoreboard vs monitor, etc
How to use muxes to implement an XOR gate?
Anything from coding to schematics to sta to low power to verification
What are some examples of scripts you have wrote, and give some scripting solutions to a problem, e.g. parsing timing reports.
What are the ways to reduce power consumption?
How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.
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