Generate a pattern 1101
Digital Design Engineer Interview Questions
820 digital design engineer interview questions shared by candidates
Filter design questions (pole/zero placement). Static Timing Analysis question between 2 clock domains. Convert this circuit into only NOR gates.
Static timing analysis and finite state machines were the major focus
What's one thing you would immediately recommend improving on the Best Buy website?
Questions from Digital Integrated Circuits and Obiected-Oriented Programming.
State machines,Timing and Critical path
factorial of a number
Asynchronous fifos, critical path timing, formal verification, clock gating
What are glitches. How would you get rid of them in a digital signal?
Given a white-board diagram of a block with a FIFO, and verbal description of the block's inputs & outputs, write on the withe board the Verilog or SystemVerilog for the design. I had 15 minutes. Why would you want someone who goes straight to code, with no planning? That usually results in spaghetti code that has to be rewritten.
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