Design a hardware for a given waveform, Verilog etc
Fpga Design Engineer Interview Questions
151 fpga design engineer interview questions shared by candidates
Design an async scrambler with various input rate, and output in a serial bitstream.
Describe FPGA design steps ? Timing constraints ? Power optimisation constraints ? Example of RTL to program in VHDL
How do you handle clock domain crossings for counters.
Using the whiteboard, show us how you would architect an FPGA to handle a proposed problem. Using the whiteboard, show us VHDL or Verilog code to implement an FSM.
timing questions, design flow questions
Write the verilog code for a divide-3 counter with 50% duty cycle.
Timing related questions, RTL design
What is your experience with random constrained stimulus?
You have a device connected with a I2C bus. You send the data to the FIFO inside this device. How can you let the master know about FIFO overflow?
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