Na reunião de RH houveram perguntas sobre as experiências profissionais anteriores e na parte técnica não houveram muitas perguntas fora os problemas propostos mas era esperado que fossem feitas análises das soluções mesmo sem perguntas serem feitas.
Fpga Design Engineer Interview Questions
151 fpga design engineer interview questions shared by candidates
What is a challenging situation that you experience in a group project?
write a clock divider in verilog
Asked about setup time, hold time violations of different circuits and also about clock domain crossing.
Technical question : questions about HDL languages as well as clock domains.
VHDL code for rising edge detector, rounding off a 24 bit number. Clock domain crossing questions. Questions on resume. Timing questions.
Multiple SystemVerilog questions were asked. No questions about VHDL were asked.
Can't remember.
What you know about the company
They asked to explained me something from my resume that matches the skills of the job description.
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