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402 ic design engineer interview questions shared by candidates

Questions on On chip variation and what causes them. Was asked how I'd model them. i mentioned timing derates -which are a very old technique. Was asked if i worked with AOCV models. Was asked few questions on clock jitter
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Senior IC Design Engineer

Interviewed at Xilinx

4.2★
Jul 16, 2018

Questions on On chip variation and what causes them. Was asked how I'd model them. i mentioned timing derates -which are a very old technique. Was asked if i worked with AOCV models. Was asked few questions on clock jitter

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