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Logic Design Engineer Interview Questions
95 logic design engineer interview questions shared by candidates
Time Diagram of AHB and ask the key points about time analysis
What is the meaning of set up time?
design an FSM that receives an array or bits and each time calculates if the received array is devisable by 3
Lots of questions were asked & was made to solve many problems based on 3 subjects above. They were more interested in your knowledge than whatever u have written in cv.
Design a full adder using only a special gate F= (not A)B+C Note: Do not use any type of gates except the special gate, we should not even use NOT gate while designing
What are Clock domain crossing techniques?
Do we need PC to index second level table of branch predictor (i.e. pattern history table)? Why? What if bits of PC more than bits to index to pattern history table?
Resume questions (describe your contributions to your projects, etc) What is a d flip-flop, setup/hold time, cache questions, algorithms (how to organize a list of names with a corresponding piece of data - eg. linked list/BST)
Design a combinational circuit that detects the number of overlapping 111 when a byte is passed serially?
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