basic questions on STA and CMOS Theory ,more on timing ,and also perl/tcl
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Questions were asked on basic digital circuits,counters and cmos power dissipation. And some puzzles and pseudo codes
How can we reduce the delay of the interconnection wire between two optimized combinational logic circuit?
PnR full form? *There will be multiple choice for the answer.
Technical question but related to the field
try to be crystal clear about setup time and hold time violation cases so that you can give quick answers to the interviewer...
1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)
should a hold buffer place close to capture flop or launch flop, why
Vlsi, setup and hold time violation, pipeline, logic design
most complicated block i have ever done in apple
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