the interviewer gave me scheme of two blocks, in the left block (block A) there were 2 FF, FFa and FFb. in block B there were only logic. FFa routed through logic to block B, and returned through logic to FFb in Block A. the interviewer tell me that is 150ns delay in the timing path between FFa and FFb, and ask me to describe what can be the cause and how to fix it.
What's constraints you gave to your design?
XOR with 2:1 MUX Edge detection Circuit Setup and hold time their violations Why do we need them what can you do to reduce them what would you do to correct s&h time after fabrication
How to resolve Placement congestion.
Logical questions are asked in interview
I cannot reveal the interview questions here , but they were practical and very interesting . You have to be strong theoretically and you should be able to apply your theoretical knowledge into the practice
a situational problems on trains
ASIC flow with all inputs and outputs for each stage.
Only basics
Basic fundamentals with in depth knowledge
Viewing 161 - 170 interview questions