4. What can be done to decrease leakage power consumption in any CMOS circuit (at least 6 points)
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Some flip flop questions, logic design questions, and static timing questions
about projects , global routing
Techniques on Cross Talk Fix?
Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?
Can Hold Time be negative and if yes why ?
What is mosfet? Region of operation of mosfet?
Can you explain the backend IC design flow?
Q1: what is the setup time and hold time? Q2: How to fix hold time violation? Q3: what will you do if you find a task you cannot fix quickly?
What i did in Engineering Question related to project Why NXP Question related to the current JOB
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