About my projects, CMOS transistors, STA
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
setup/hold in depth questions. in FF and latch with skew.
Implement a box that gets 2 bits (a and b) and has 3 outputs. The first output gets logic 1 if a>b otherwise zero The second output gets logic 1 if a=b otherwise zero The third output gets logic 1 if a
based on CTS, floorplan, STA
Tell me about your Self and Synthesis, STA Technical Questions. Timing Closure on Block and Chip Level.
What is JTAG What is cluster based design? Describe about cluster based region? 2. What are the problems are faced when placing long net of FF to FF path and Short net of FF to FF path? 3. Is timing driven placement advantageous over the functionality based placement? Explain briefly. 4. Explain In Place Optimization and Timing Delay? 5. How to do Congestion optimization and balance slew?
CMOS Inverter , how to reduce the drive strength of Minimum size inverter
They asked me mainly about digital circuits and in VLSI the emphasis was mainly on cmos technologies
Digital electronics, synthesis, physical design and Linux commands and tickle, if any scripting languages related to hardware language
1.design a circuit using FA and HA which finds the number of ones in the six bit number
Viewing 601 - 610 interview questions