Noise margin in CMOS, Regions of operation in CMOS
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Told to design a layout through a very slow laptop, be prepared. asked about parasitics in layout design, and effect of high voltage on MOS and what should you do.
Previous challenges as a physical design engineer, lot of questions about the .libs and encounter commands.
1. project experience 2. technical questions related to PD
Scripting skills in Perl : regular expressions Logical Effort, Projects done in Master's
most of the qs are on mesh analysis, analog
Draw Full and half adder circuits. Draw a 4-bit adder circuit. Draw 2 state counter. Draw NAND gate using CMOS. What is logical effort? What are LVT cells and how does leakage is affected using them? Solving some Gate-based and Boolean algebra-based questions.
Starting from basics about Physical designing to in-depth questions related to the position
Setup-Hold timing inter-relationship question, framed by way of max frequency of operation
Provided a waveform and asked to design a circuit for that.
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