Hold time related stuff
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
1. What are the physical cells available during the pre-placement stage? 2. What are the function of those physical cells. 3. How do you fix timing hold violation? 4. How do you fix congestion?
Setup & hold time, RC impact, tran & cap fixing?
What are the preliminary checks before starting physical design implementation, after getting the netlist from synthesis team?
What is CMP polishing What is Antennas Difference between FF and Latch, Explain project from resume Explain CMOS inverter
Commands for what ever u have done?
How can you detect the loop in single way linked list, using just one extra pointer?
What happens if Bit lines are at a higher potential (let's say 1.5 V) than word line (at 1 V = logic 1) while we try to read?
NAND's input vector control to reduce leakage
Main topics asked were 1) Low power 2) Project based 3) CMOS Theory 4) Floorplanning, Placement 5) LEC 6) Timing, ECO
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