Cache coherency, reorder buffer, memory hierarchy, register renaming, data hazards.
Rtl Design Engineer Interview Questions
212 rtl design engineer interview questions shared by candidates
Mainly related to best techniques for hardware design and algorithms
Do latches have Metastability?
What is the difference between latch and flop?
Based on memories, digital design, Verilog coding
What is your productive skill
Explain each state in a mesi protocol.
Know the 5 stage pipeline well
Software (OOP, efficiency, data structures), Computer Architecture (cache coherency, pipelining), Logic (k maps, simplifying boolean expressions), and Verification (coverage, how to test, previous experience)
What is blocking and non blocking statement
Viewing 151 - 160 interview questions