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Rtl Design Engineer Interview Questions
212 rtl design engineer interview questions shared by candidates
Code of synchronous fifo in verilog code
Was asked about complex adder implementations.
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Describe cmos inverter on ramp input
Basic Digital Electronics questions related to counters
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question about architectures, questions based on cv, why you want to work for imagination.???
1. Counters 2. CDC and type of Synchronizer 3. Sync FIFO
Basic RTL codes and degital design,fsm state digram(melay andMoore state machine).setup and hold time.latch and d flip flop.synchronous vs asynchronous fifo.syncronohs reset and asynchronous reset verilog code .static timing analysis
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