Draw Cmos inverter.What would happen if we swap Pmos and Nmos.What if Nmos is connected to VDD. Questions regarding .lib,LEF, Antenna file content . How do we define rectilinear polygon in LEF.. Multicycle Path calculation for setup and hold . Draw 4 Input NAND Gate using 2 -Input NAND Gate what is index table defined in .lib file. How do we define antenna rules in techfile What are all challenges faced in your recent project. Questions were more from your resume. Any scripting which is hard for you. Tell us more about colored flow.
Senior Design Engineer Interview Questions
1,071 senior design engineer interview questions shared by candidates
Current mirror pole and zero?what ratio?
Differential pair and current mirror mismatch concern and tuning
Timing closure. How noise(cross-talk) affect setup/hold? How metal dimension affect timing?
None. Only basic questions.
Why do you want to join cirrus?
What is the saturation current formula of the MOSFET?
1) About managing the ODM 2) Handling SW issues with the projects 3) Time management
There were no difficult questions.
for one instance -- how to floorplan the layout design from this information of the IC Schematic
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