Difference between copy/clone methods in UVM
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Questions on UVM concepts like sequencer driver communication, monitors , scoreboards and coverage
Can we override constraints like data members?
Why do we need a virtual interface?
SV, V, UVM, Problem solving, Advanced formal verification based questions, experience based questions
In SystemVerilog: Write the code for stepping through a circular array. Also, how would you initialize a multi-dimensional array?
Various Verilog detailed questions. I had about 3 months experience of Verilog some 8 years ago. I can't remember the details of the questions.
The interviewer was from a different background, hence there wasn't any question-answer session
Asking abut the technical question.
Describe the entire verification cycle of a particular block testing.
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