What is the effect on delay when an inverter input is connected to 10 inverters and output is connected to a few more inverters?
Technical Design Interview Questions
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what is the total noise at the output of an ideal integrator
12V source in series with 3 caps of so and so capacitance, the last of which is hooked to gnd. If node between the first and 2nd cap is initially open, then closed, what are the node voltages.
What's the advantage of one-hot coding
You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup, T_hold, etc. How to determine the cycle time and hold time of this circuits.
Compare the power usage of a regular versus a gray code counter.
How to detect voltage source and current source in a black box
Difference between a latch and a flipflop
What is setup hold time
why is matching required?
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