Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
Verification Design Engineer Interview Questions
1,114 verification design engineer interview questions shared by candidates
The questions in the first interview were mostly about C semantics and rules. Nothing fancy, but you should know the nuances of the language.
Waiting for interview to be held. Will update once done
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
Introduce the experience you have related to verification.
System verilog, UVM scoreboard/monitor coding
Q1: verification plan for a stated scenario
1. Some simple random stimulus with specified constraints
They asked me to sort an array with an specific condition, without sorting
Define verilog ,systemverilog. Memory /cache
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