Asked to explain the different BFM's i worked on and few questions on them.
Verification Design Engineer Interview Questions
1,114 verification design engineer interview questions shared by candidates
Write SV assertion for a req/ack protocol
everything about SV and UVM.
What are the UVM phases
Timing analysis calculation for a digital block -
describe D flipflip in combinational circuit
Construction of or gate using mux 2x1
Basics of Uvm to advanced gone from stage by stage increasing the difficulty.
what is bjt and what it is used for
ready to relocate to odissa?
Viewing 161 - 170 interview questions
See Interview Questions for Similar Jobs
Fpga Design EngineerVerification EngineerRtl Design EngineerVlsi Design EngineerLogic Design EngineerPhysical Design EngineerCpu Design EngineerElectrical Product Design EngineerSenior Vlsi Design EngineerSenior Fpga Design EngineerVerification ManagerSenior Asic Fpga Design EngineerApplication Design EngineerHardware Design EngineerSenior Physical Design EngineerIc Design EngineerFpga Development EngineerAsic Verification Engineer