About system verilog , verilog, digital electronics
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
Sorting, bit logic
How do you find common elements between the arrays? reduce the complexity, asked me to write the code
What is the scope of a static variable? Given multiple scenarios(static variables across files, in recursion, ect.)
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
class A; function int foo(); int a; return ++a; endfunction endclass program tb; A a; int b, c; initial begin for(int i = 0; i < 10; i++) begin b = a.foo(); c = foo(); $display("B = %0d", b); $display("C = %0d", c); end end function int foo(); int a; return ++a; endfunction
design question - design a system to identify if input bitstream is divisible by 5 - taking a 16bit stream, programming - print matrix spiral, etc. Also assertion questions, UVM
Tell me a bit about yourself.
Immediate vs. Concurrent Assertions .
What is a pipeline driver?
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