Design, Test plan, SystemVerilog ......
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
how to resolve the issue with a malfunctioning vending machine with a pending deadline
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
How to use muxes to implement an XOR gate?
Delayed assignment and delayed evaluation in Verilog
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
Resume questions, fifo questions, assertions, coverage
General questions in Python, C, Verilog, and SystemVerilog.
1. About the company, why apple 2. About projects as per resume-interesting test case, negative test case 3. different types of Hazard and how to avoid those 4. pipelining concept 5. Problem-solving: (using associative array-)how to sort names without repetition
CDC, HW design, testbench engineering, etc..
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