Verilog Design and verification related
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
Are you familiar with System Verilog
What products of the company do you know? tell me a project you have done in the past and what did you learn form it..what would you change.. write 2 little projects in VHDL or Verilog (a state machine and a counter).. explain what you did..
Some basic questions/tasks about C programming (pointers, arrays..), design task for receiving data bytes from the transmitter (C programming), Asked to explain different parts of some old SOC configuration. For people studying only Electronics I would suggest going through Software Engineering lectures from other courses to know about how memory is managed in a SOC and CPU. Ideally read about the Architecture of CPU and Microcontrollers as I was asked this in all 3 Interviews with ARM. I only studied Electronics and had no courses related to this except when we briefly looked into simple microcontrollers without going into detail so it was good decision going through Software Engineering course notes before the interview.
Decode a CMOS transistor diagram (complex)
Few puzzles and Projects in my resume
That's all i can share . Practice your basics. All the best !
Questions related to pipelining, hazards, in-order processor, out of order processor, Register renaming, branch prediction, caches and virtual memory
Teamwork that related to the position.
UVM concepts, assertions, tb arch
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