What is Stratified Event Queue
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
Basic to twitsed questions in sv and uvm
What is overriding method? What is blocking and non blocking assignment?
Define setup and hold time and define the maximum operating frequency of a digital synchronous circuit?
1. What is setup, hold time. Reason of metastability. 2. How to reduce setup time, hold time. 3. A C code to check if a given number is divisible by 2 4. Difference between mealy and moore machine 5. Project and resume based questions
Questions on GATE level questions all digital electronics
Design an 1×4 demux using 2×1mux
Write code for asynchronous D flip-flop.
About projects and Static timing analysis
No one show up for the interview
Viewing 581 - 590 interview questions
See Interview Questions for Similar Jobs
Fpga Design EngineerVerification EngineerRtl Design EngineerVlsi Design EngineerLogic Design EngineerPhysical Design EngineerCpu Design EngineerElectrical Product Design EngineerSenior Vlsi Design EngineerSenior Fpga Design EngineerVerification ManagerSenior Asic Fpga Design EngineerApplication Design EngineerHardware Design EngineerSenior Physical Design EngineerIc Design EngineerFpga Development EngineerAsic Verification Engineer