Sv constraints on memory block and region. GLS questions on debug flow.
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
Develop a C algorithm to solve arbitration in bus
How instructions are executed in assembly language? How data is transferred between cpu and cache? Why we need cache, why we don't use main memory? Why cache size is kept small?
can you describe what you worked on in your project, biggest roadblock?
For the design verification interview, I haven't prepared at all since I didn't know that it was a verification position, all the questions about programing were not answered well.
Basics of Digital System Design and Analog Electronics.
Calculate address lines required for memory. Puzzle . FIFO verification test cases. Why computer engineering
Basics of computer architecture, verification, data structures, rtl logic Telephonic interview was basics of RTL design
question on packet transfer inside of test bench from generator to driver... (system verilog concepts)
There were 4 rounds - 3 technical and 1 HR.
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