I was asked to write system verilog constraints for a variety of random stimulus needs.
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
Questions on C++, Perl, System Verilog.
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Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
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questions on digital electronics and verilog
Pipeline , caches, TLB , virtual memory
Why is program block needed. What is clocking block. Program for clock without always. Differnce between always_combo and always.
What is your experience with random constrained stimulus?
When in your previous work did you wish you behaved differently?
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