Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
Verification Engineer Interview Questions
Verification Engineer Interview Questions
Companies rely on verification engineers to ensure that their products work as intended. Prepare to answer questions that will assess your ability to design and implement product testing methods. Expect the interviewer to evaluate your communication and documentation skills, essential when working with product designers.
Top Verification Engineer Interview Questions & How to Answer
Question #1: What skills should a successful verification engineer possess?
Question #2: What information do you need to develop a product test methodology?
Question #3: What techniques do you use when developing a product test?
3,814 verification engineer interview questions shared by candidates
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
Tell me about yourself and your skills
c++ basics - virtual functions, function vs task difference, coverage , constraints
Verilog code for basic circuits
Can we override constraints like data members?
Why do we need a virtual interface?
write assertions for the given timing diagram
SV, UVM, Driver sequencer handshake mechanism
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