Companies rely on verification engineers to ensure that their products work as intended. Prepare to answer questions that will assess your ability to design and implement product testing methods. Expect the interviewer to evaluate your communication and documentation skills, essential when working with product designers.
Draw simple NMOS current mirror. what are its disadvantages and how do you overcome it . what is the new topology and swing across output node. and another topology if you have any problem with current topology. they asked sinking current mirrors too
Round 1: resume projects(in detail, my role and contribution), basics like cmos inverter, cmos nand gate, current mirror, blocking vs non blocking, explained a design and asked for the verilog code of it. Round 2: Linux, Python regular expressions. I could not answer linux and python questions so he asked me to explain the logic instead of writing the code. 45 mins break Round 3: She wanted to know how well I was aware of Analog design basics. Virtual interface, inertial vs transport delay, how to debug errors in simulator, asked about the tools I mentioned in the resume. Round 4: Lots of verilog, digital basics, gave a black box and asked how can I verify it if there were two sub modules one analog and one digital. Clock gating and how can we get clock gating, basic building block of counters, inertial vs transport delay, verilog vs SV, . Round 5: It was more like a discussion on a verification plan with analog and digital modules. Round 6: With the manager, behavioral questions, how do you deal with stress, how did you manage people in your previous job, how do you deal with people who always comment, why do you want to get hired for this role even though you do not have enough skills.
Verilog code for the clock divider Verilog code for clock generator for a particular frequency Same basic Verilog and System Verilog questions.
Difference between m sequencer and p sequencer in uvm?
counter design, fsm, probability, verilog
Write UVM driver/monitor Come up with a test plan Write constraints
Focus a lot on sv
What are the performance tradeoffs of different cache architectures?
Coding the basic skeleton code for a given design. All UVM components should be coded and explained. This includes monitors, scoreboard logic, dut, agents , sequence items, sequence , driver and test
Questions on basic debugging skills using synopsys VCS. OOP concepts. Ethernet , AXI, APB protocols and their usage. Protocol bridge
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