Companies rely on verification engineers to ensure that their products work as intended. Prepare to answer questions that will assess your ability to design and implement product testing methods. Expect the interviewer to evaluate your communication and documentation skills, essential when working with product designers.
Round 1: 1. What is Functional Verification? Round 2: 1. What is the difference between Verilog and System Verilog? 2. What is the difference between Blocking and Non-Blocking assignment? 3. What is an FSM 4. Mealy and Moore machine 5. What is the difference between synchronous and asynchronous design? 6. Verification using test environment 7. UVM testbench 8. Synthesis design model 9. Critical path 10. Setup time and Hold time 11. Metastable state And some more verification related stuff
Formal verification basics, writing assertions, etc.
Uvm related Project related Sv concepts Fifo full empty conditions Fork join concepts Axi ahb difference
find the minimal number of semi-binary numbers that sum up to a given number. semi-binary is an integer that is composed only by the digits 1 and 0.
HR interview were standard questions. Interview with manager were more technical and based on testing and previous experiences
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Nothing unexpected
Computer Architecture, Logic design, validation, software, behavioral.
Black-box vs white box testing, techniques used while verifying designs, system verilog constructs related to verification, UVM OVM etc
Difficult technical questions, very unforgiving when I got one question wrong, they ended the interview straight away after that.
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