Questions were asked on verilog and system verilog. Some famous puzzles and aptitude questions were asked. In manegerial round my errors of written round were discussed.
Verification Engineer Interview Questions
Verification Engineer Interview Questions
Companies rely on verification engineers to ensure that their products work as intended. Prepare to answer questions that will assess your ability to design and implement product testing methods. Expect the interviewer to evaluate your communication and documentation skills, essential when working with product designers.
Top Verification Engineer Interview Questions & How to Answer
Question 1
Question #1: What skills should a successful verification engineer possess?
How to answer
How to answer: This question gives you the chance to demonstrate that you understand what the role entails, while showcasing your specific skills. A concise answer that clearly illustrates your approach to verification engineering will signify your value to the interviewer and the company.
Question 2
Question #2: What information do you need to develop a product test methodology?
How to answer
How to answer: Use this question as an opportunity to demonstrate your communication skills and your ability to work with a team. Make it clear to the interviewer that you value input from the product designers and that you don't hesitate to ask questions when necessary. The interviewer will also assess your analytical skills when you answer this question. Explain your information-gathering process and how you apply that information as concisely as possible.
Question 3
Question #3: What techniques do you use when developing a product test?
How to answer
How to answer: Prepare to demonstrate that you are familiar with a range of verification engineering techniques. Make sure you mention methods specific to the products produced by the company you're interviewing with.
3,806 verification engineer interview questions shared by candidates
UVM question : Assuming, UVM environment has 3 different agents having scope to their own interfaces. On driving wrong stimuli on agent1, there will be error pin asserted on interface3(monitor of agent2 sees this). soon after error-pin assertion, there should be a read transaction from agent2. How do you make sure your agent2 drives a read transaction on every wrong stimulus from agent1, which was seen on a monitor of agent2 ?
Implement a 10:1 mux using 3 4:1 muxes
1. If the input number is 4 return 7 and if input number is 7 return 4 without using if condition or switch statements. 2. Given a number, return the index of the first occurrence of bit 1. 3. There are 2 given linked lists, add them and store the result in result linked list Ex: l1:9->5->9 l2:4->6 result:1->0->2->3 4. Tell me about yourself
First interviewer did bus connection verification. so he asked about the protocol of ahb and axi. Then he asked how many vip should be used for their verification environment. I didn't understand the question clearly. Because if we want to keep CPU and the code run on real CPU, we don't need to replace these interfaces with VIPs, but if the CPU needs to be replaced, only other slave/master interfaces need to be replaced by VIPs. After he cleared it, what he wanted to do was to replace all the CPU interfaces and other IP interfaces. The second interviewer asked 2 questions: 1) how to check the module was reset by reading/writing registers? The premise for this was there was no spec for register. 2) how to check an interrupt was generated? There was a bit in the register for the interrupt signal. The third interviewer asked the following questions: 1) virtual memory structure 2) spin lock 3) tomasulo 4) fibonacci generator The last technical interviewer asked: 1) shell questions: search a key word in a file and count how many lines contain the key word 2) Perl sort question: user perl to sort a hash with key or with value 3) set environment variable in Perl 4) fibonacci generator 5) there are 2 buckets: 5 litters and 3 litters, how to get 4 litters of water 6) there is a rectangle pie, remove a small rectangle in that large rectangle, after that, use a straight line to cut the pie to get 2 equal areas. There was another question I forgot who asked: use SystemVerilog to generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) ...
Some technical/coding questions: Swap the value of variable A and B without using a third variable
(Unexpected) What the types of caches?
Given integers from 0-100 stored in an array of size 100 how will you find the missing number? Numbers are randomly entered in the array.
Write the base-11 representation of the decimal number 175.
The topics are given before hand so that you can study.
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