Build a verification environment to an ordering block.,what woukd be generation and coverage like.
Verification Interview Questions
3,815 verification interview questions shared by candidates
Basics of digital, verilog, system verilog and uvm.
tell about your previous projects
First there was some basic questions on Computer Architecture, Verification Concepts and RESUME. After that she asked me to write code for hamming distance in prefered lang and UVM Code for driver component.
System verilog syntax
What's C++ STL
Given this design and their features, explain how you would build a UVM testbench to verify it.
What is a state machine?
A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
How to verify your design ？about testbench design ...
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