What is the difference between strong and weak memory models?
Verification Interview Questions
3,807 verification interview questions shared by candidates
1) Swap in Verilog 2) Print 2D matrix spirally starting from centre 3) randomize the size of a 2D matrix/multi dimentional array 4) Fork-join and how to disable fork 5) Assertions 6) Reverse a string 7) How to verify a vending machine 8) Application of UVM Barrier class, 9) Divide by 5 state machine and extract a mathematical equation to generate the next state , 10) Write a system verilog test to verify if all the clocks on the SOC have been switched off after writing 'b1 to a register , 11) Why do we need UVM agents , 12) How is UVM Scoreboard implemented, 13) Constraint address to word accessible , atleast 2 ways to do it , 14) Test Plan and functional Coverage
2nd phone interview: 1 unit with 9ns delay vs 3 units with delays 2ns, 4ns, 3ns. Which has better throughput and how much?
You have an array of integers. How would you find the maximum value?
explain me why uvm methodology ?
UVM Phase, Mail box in SV
Types of hazards. What is TLB.
What are the five stages of pipelining?
Design a system to detect binary 0110?
What is the difference between intra and inter assignment delays?
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