How would you debug a failing simulation where coverage is not met?
Verification Interview Questions
3,813 verification interview questions shared by candidates
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why should i hire you
What has been your least favorite job?
Basic question in SV, UVM, Verilog, Linux
Why I would be an ideal candidate for the position that I had not previously done before, and what would I bring to the company?
Why Kindred?
Describe the voltage response of a circuit consisting of a current source in series to a switch and a (capacitor parallel to another switch) when each switch is closed.
1. UVM testbench-related concepts like a factory, the handshake between sequencer and driver, etc... 2. Projects-related questions on cryptography, AXI-stream, AXI-4, and APB protocols.
Generic Verification questions and some sample codes
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