Write code for a UVC mimicing a memory . Reactive sequence in UVM
Verification Specialist Interview Questions
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1) C++ code to set the matrix MxN to zero if any element in MxN is zero. (leetcode medium question) 2) write constraint to set 32 bit address to be word aligned and 1kb in length
For the first screening round, all questions were based on out-of-order execution CPU. For the final interview, In 1st round, I was asked questions on out-of-order execution CPU 2nd round on cache and virtual memory 3rd round had one coding question based on queues and cache-related questions
Print smallest of three numbers
how to design a FSM using switch-case / shift register
How can you swap two numbers without using an extra temporary variable? Note that each variable is limited by a certain number of bytes
do I know objective-oriented coding
Verification plan of any given design, assertions, what is coverage?
* Have you used UVM? * What is your knowledge level of SystemVerilog?
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