what 's the steps of synthesis?
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Questions on Flip-flops, tristate buffer, logic design
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Asked on how to care of Hold time & Setup time
Design a two input XOR gate use 1 MUX.
Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.
Write UVM Monitor for the defined case.
Asynchronous FIFO full empty
ASIC Design
How would you go about verifying a design?
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