What would be behavior of a CMOS inverter if the nMOS and pMOS are interchanged?
Asic Design Engineer Interview Questions
810 asic design engineer interview questions shared by candidates
Design a circuit that would count 1 every time another counter counts from 0 to 255. One of the counter is working at higher frequency than the other.
(Unexpected) What the types of caches?
Suppose you discover that the circuit you are testing in the lab does not function correctly due to a hold time violation. What would be the first thing you try to make the circuit work?
Suppose you have an infinite bit stream representing a binary number (LSB first), and that stream is entering your machine one bit per clock cycle, and you want your state machine to output a 1 any time the total is divisible by 5, otherwise output zero.
using a simple logic gate, convert a SET type flop to a RESET type flop
How to check if a fabricated chip has a hold time violation, and how to fix it.
calculate the addressing of a 4-way set associative cache for a given size
The second questions is about Combination logic, to conter the first 1 bit in the 8192 data stream. the output it in 13-bit index. it is a little difficult!
there is a disk half painted white and the other half black. There are two sensors and the outputs of these sensors are the only signals available. How will you determine if the disk is rotating clockwise or anti-clockwise?
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