basic of digital, verilog sta, fsm
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Implement a Hardware based LRU scheme for a 4-way set associative cache.
About UVM phases and how I use them.
Can you explain common centroid layout?
Talk about two projects you have done in university. What is your contribution.
The skype interview was too technical and to ASIC-oriented. I work for 4 years. At the end of University I could answer it, now I forgot a lot...
Walk through past designs, clock crossings, some scenarios just the usual but nothing that was out of line for the position
Asked basics
reorder buffer store pointer.
1.How to deal with multi-bit CDC 2.How to analysis timing for clock gating cell 3.Synthesis flow
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